The present invention relates to a semiconductor memory device, and more particularly, to a delay-locked-loop control circuit and a method of controlling a delay-locked-loop.
In general, a semiconductor memory device uses a variety of control methods to effectively manage current consumption.
Among them, a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like are few control methods for effectively managing current consumption related to operations of a delay-locked-loop, which compensates for a skew between an external clock and data, or an external clock and an internal clock.
Here, the self-refresh emulation mode means a mode, which operates similarly to a self-refresh by combining a pre-charge power-down operation and an auto-refresh operation.
FIG. 1 is a waveform diagram illustrating the control operation of a delay-locked-loop in a power-down mode. Referring to this, when a clock enable signal (CKE) falls to a low level, it is synchronized at a next rising edge of an external clock (CLK), and a power-down signal (PWDN) is enabled.
If the power-down signal (PWDN) is enabled, a semiconductor memory device enters into a power-down mode, and particularly in case of a pre-charge power-down mode, which enters into a power-down mode when all banks are in a pre-charge state, a delay-locked-loop is turned off or enters into a standby state to reduce the current consumption of the memory chip.
In other words, if the power-down signal (PWDN) is enabled when all banks are in a pre-charge state, a signal (DLL_ON) for turning on the delay-locked-loop by the power-down signal (PWDN) is disabled, and the delay-locked-loop is turned off or enters into a standby state.
Similar to this, also in a self-refresh mode, the delay-locked-loop is turned off or enters into a standby state by a self-refresh command, thereby reducing the current consumption by the delay-locked-loop.
At this time, if the power-down mode or the self-refresh mode is maintained for a long time, or a change occurs in the power or the like, malfunction may occur since the delay-locked-loop cannot perform an update sufficiently.
Looking into this in detail with reference to FIG. 2, the specification for a self-refresh mode specifies that, a chip is accessible after a duration of ‘tXSNR (Exit Self Refresh To A Non-Read Command time)’ if a read command is not inputted, and a chip is accessible after a duration of ‘tXSRD (Exit Self Refresh To A Read Command time)’ if a read command is inputted.
The ‘tXSNR’ can be defined as ‘tRFC (Refresh To Active/Refresh Command time)+10*tCK’, and the ‘tXSRD’ can be defined as ‘200*tCK’.
However, a chip can be accessed faster in a self-refresh emulation mode than in the self-refresh mode. In other words, a chip can be accessed ‘tXP (Exit Precharge Power-Down To Any Non-Read Command time)’ later when a read command is not inputted, or ‘tXPRD (Exit Precharge Power-Down To Read Command time)’ later when a read command is inputted.
Here, the ‘tXP’ can be defined as ‘2*tCK’, and ‘tXPRD’ can be defined as ‘tXP+tRCD (RAS To CAS Delay)−AL (Additive Latency)’.
A refresh operation can progress as an internal operation of the memory chip even if an auto-refresh command (‘A’ of FIG. 2) is inputted during a high interval of the clock enable signal CKE.
Accordingly, in the self refresh emulation mode, a case may occur that it is maintained high for a minimum pulse holding time of the clock enable signal CKE, ‘3* tCK’, and then maintained low for ‘tREFI (Average Periodic Refresh Interval).’
In this case, a high interval of the clock enable signal CKE, which is a possible interval for updating the delay-locked-loop, is very short, and the update time of the delay-locked-loop (typically, a time between ‘5*tCK’ and ‘20*tCK’) is not sufficiently ensured, thereby causing a malfunction of the delay-locked-loop, and accordingly there is a problem that data may not be normally outputted.